COMPUTER ARCHITECTURE

Computer Architecture

Computer  Architecture is the design and internal organization of a computer system to meet its requirements, as efficiently as possible, within technology and cost constraints. Simply adding more resources to a computer system does not always make it faster, especially when the main limit is power consumption. Computer architecture addresses all levels of the computer system, from the core, chip, memory, board, to the whole system and its interconnect.  Finding the right balance in the design and proposing new design alternatives are key tasks of the computer architect.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. Instruction set architecture is distinguished from the micro architecture,

which is the set of processor design techniques used to implement the instruction set. Computers with different micro architectures can share a common instruction set.

 For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instructions set, but have radically different internal designs.

Classification of Instruction Sets

A complex instruction set computer (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A reduced instruction set computer (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use. Theoretically important types are the minimal instruction set computer and the one instruction set computer, but these are not implemented in commercial processors. Another variation is the very long instruction word (VLIW) where the processor receives many instructions encoded and retrieved in one instruction word. Machine language is built up from discrete statements or instructions. On the processing architecture, a given instruction may specify:

1. Particular registers for arithmetic, addressing, or control functions
2. Particular memory locations or offsets
3. Particular addressing modes used to interpret the operand

More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by control flow instructions. The design of instruction sets is a complex issue. There were two stages in history for the microprocessor.
The first was the CISC (Complex Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions.
A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory/cache efficiency, or simplify programming. Reduced instruction-set computers, RISC, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register.
 A RISC instruction set normally has a fixed instruction width, whereas a typical CISC instruction set has instructions of widely varying length.

However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.

Characteristics of CISC Architecture

1. Instruction-decoding logic will be Complex.
2. One instruction is required to support multiple addressing modes.
3. Less chip space is enough for general purpose registers for the instructions that are 0operated directly on memory.
4. Various CISC designs are set up two special registers for the stack pointer, handling interrupts, etc.
5. MUL is referred to as a “complex instruction” and requires the programmer for storing functions.

RISC Architecture Characteristics

1. Simple Instructions are used in RISC architecture.
2. RISC helps and supports few simple data types and synthesize complex data types.
3. RISC utilizes simple addressing modes and fixed length instructions for pipelining.
4. RISC permits any register to use in any context.
5. One Cycle Execution Time
6. The amount of work that a computer can perform is reduced by separating “LOAD” and “STORE” instructions.
7. RISC contains Large Number of Registers in order to prevent various number of interactions with memory.
8. In RISC, Pipelining is easy as the execution of all instructions will be done in  a uniform interval of time i.e. one click.
9. In RISC, more RAM is required to store assembly level instructions.
10. Reduced instructions need a less number of transistors in RISC.
11. RISC uses Harvard memory model means it is Harvard Architecture.

RISC & CISC Comparison

The Advantages of RISC Architecture

1. RISC(Reduced instruction set computing)architecture has a set of instructions, so high-level language compilers can produce more efficient code
2. It allows freedom of using the space on microprocessors because of its simplicity.
3. Many RISC processors use the registers for passing arguments and holding the local variables.
4. RISC functions use only a few parameters, and the RISC processors cannot use the call instructions, and therefore, use a fixed length instruction which is easy to pipeline.
5. The speed of the operation can be maximized and the execution time can be minimized.
6. Very less number of instructional formats, a few numbers of instructions and a few addressing modes are needed.

The Disadvantages of RISC Architecture

1.  Mostly, the performance of the RISC processors depends on the programmer or compiler as the knowledge of the compiler plays a vital role while changing the CISC code to a RISC code while rearranging the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set. The first level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.

Advantages of CISC Architecture

1. Microprogramming is easy assembly language to implement, and less expensive than hard wiring a control unit.
2. The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible:
3. As each instruction became more accomplished, fewer instructions could be used to implement a given task.

Disadvantages of CISC Architecture

The performance of the machine slows down due to the amount of clock time taken by different instructions will be dissimilar. Only 20% of the existing instructions are used in a typical programming event, even though there are various specialized instructions in reality which are not even used frequently. The conditional codes are set by the CISC instructions as a side effect of each instruction which takes time for this setting and, as the subsequent instruction changes the condition code bits the compiler has to examine the condition code bits before this happens.

BRANCH INSTRUCTION: A branch is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order. Branch (or branching, branched) may also refer to the act of switching execution to a different instruction sequence as a result of executing a branch instruction. A branch instruction can be either an unconditional branch, which always results in branching, or a conditional branch, which may or may not cause branching, depending on some condition. Branch instructions are used to implement control flow in program loops and conditionals (i.e., executing a particular sequence of instructions only if certain conditions are satisfied).

The term branch can be used when referring to programs in high level languages as well as program written in machine code or assembly language. In high-level programming languages, branches usually take the form of conditional statements of various forms that encapsulate the instruction sequence that will be executed if the conditions are satisfied. Unconditional branch instructions such as GOTO are used to unconditionally "jump" to (begin execution of) a different instruction sequence.

Performance Problems with Branch Instructions

To achieve high performance, modern processors are pipelined: they consist of multiple parts that each partially process an instruction, feed their results to the next stage in the pipeline, and start working on the next instruction in the program. This requires knowing which instruction is going to be executed next, and (conditional) branch instructions make it impossible to know this in general, thus potentially causing stalls where the pipeline has to be restarted on a different part of the program.

Two techniques alleviate this situation. The first is branch prediction, which is implemented as part of modern processors. The processor attempts to guess the outcome of the conditional test and starts executing the branch that it thinks is going to be taken. The other technique is to write programs without branches, or with fewer branches, typically using bitwise operations instead.

Parallel & Serial Transmission 

In telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels.
Serial Communication is used for all long-haul communication and most computer networks, where the cost of cable and synchronization difficulties makes parallel communication impractical. Serial computer buses are becoming more common even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect density). Many serial communication systems were originally designed to transfer data over relatively large distances through some sort of data cable.
The term ‘serial’ most often refers to the RS232 port on the back of the original IBM PC, often called the serial port, and the serial cable designed to plug into it, and the many devices designed to be compatible with it. Practically all long-distance communication transmits data one bit at a time, rather than in parallel, because it reduces the cost of the cable. The cables that carry this data (other than "the" serial cable) and the computer ports they plug into are usually referred to with a more specific name, to reduce confusion. Keyboard and mouse cables and ports are almost invariably serial -- such as PS/2 port and Apple Desktop Bus and USB.
PARALLEL COMMUNICATION is a method of conveying multiple binary digits (bits) simultaneously. It contrasts with serial communication, which conveys only a single bit at a time; this distinction is one way of characterizing a communications link. The basic difference between a parallel and a serial communication channel is the number of electrical conductors used at the physical layer to convey bits. Parallel communication implies more than one such conductor. For example, an 8-bit parallel channel will convey eight bits (or a byte) simultaneously, whereas a serial channel would convey those same bits sequentially, one at a time.

If both channels operated at the same clock speed, the parallel channel would be eight times faster. A parallel channel may have additional conductors for other signals, such as a clock signal to pace the flow of data, a signal to control the direction of data flow, and handshaking signals.

PARALLEL COMMUNICATION is and always has been widely used within integrated circuits, in peripheral buses, and in memory devices such as RAM. Computer system buses, on the other hand, have evolved over time: parallel communication was commonly used in earlier system buses, whereas serial communications are prevalent in modern systems.  Intuitively, one would think that parallel data transmission should be faster than serial data transmission; in parallel bits are transferred all at the same time, whereas in serial you are doing one bit at a time.
So what makes SATA interfaces faster than PATA, PCI-e devices faster than PCI, and serial ports faster than parallel? Serial transmission is slower than parallel transmission given the same signal frequency. With a parallel transmission you can transfer one word per cycle (e.g. 1 byte = 8 bits) but with a serial transmission only a fraction of it (e.g. 1 bit).

The reason modern devices use serial transmission is the following:

1. You cannot increase the signal frequency for a parallel transmission without limit, because, by design, all signals from the transmitter need to arrive at the receiver at the same time. This cannot be guaranteed for high frequencies, as you cannot guarantee that the signal transit time is equal for all signal lines (think of different paths on the main board). The higher the frequency, the more tiny differences matter. Hence the receiver has to wait until all signal lines are settled -- obviously, waiting lowers the transfer rate.
2. Another good point (from this post) is that one needs to consider crosstalk with parallel signal lines. The higher the frequency, the more pronounced crosstalk gets and with it the higher the probability of a corrupted word and the need to retransmit it.

 So, even if you transfer less data per cycle with a serial transmission, you can go to much higher frequencies which results in a higher net transfer rate. This also explains why UDMA-Cables (Parallel ATA with increased transfer speed) had twice as many wires as pins. Every second wire was grounded to reduce crosstalk.

Open & Closed Architecture 

Open architecture is a type of computer architecture or software architecture that is designed to make adding, upgrading and swapping components easy. For example, the IBM PC and Apple IIe have an open architecture supporting plug-in cards, whereas the Apple IIc and Amiga 500 computers have a closed architecture. Open architecture systems may use a standardized system bus such as S-100, PCI or ISA or they may incorporate a proprietary bus standard such as that used on the Apple II, with up to a dozen slots that allow multiple hardware manufacturers to produce add-ons, and for the user to freely install them. By contrast, closed architectures, if they are expandable at all, have one or two "expansion ports" using a proprietary connector design that may require a license fee from the manufacturer, or enhancements may only be installable by technicians with specialized tools or training.
 Computer platforms may include systems with both open and closed architectures. The Mac mini and Compact Macintosh are closed; the Macintosh II and Power Macintosh G5 are open. Most desktop PCs are open architecture, but nettops are typically closed. Open architecture allows potential users to see inside all or parts of the architecture without any proprietary constraints. Typically, an open architecture publishes all or parts of its architecture that the developer or integrator wants to share. The open business processes involved with an open architecture may require some license agreements between entities sharing the architecture information. Open architectures have been successfully implemented in many diverse fields.

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